The present application relates to semiconductor devices, and particularly to power semiconductor devices which use intentionally introduced permanent electrostatic charge in trenches which adjoin regions where current flows in the ON state.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize the conduction power loss it is desirable that power MOSFETs have a low specific on-resistance (RSP or R*A), which is defined as the product of the on-resistance of the MOSFET multiplied by the active die area. In general, the on-resistance of a power MOSFET is dominated by the channel resistance and the drift region resistances which include the substrate resistance, spreading resistance and the epitaxial (epi) layer resistance.
Recently, the so called super-junction structure has been developed to reduce the drift region resistance. The super-junction structure consists of alternating highly doped p-type and n-type pillars or layers. For a given breakdown voltage, the doping concentrations of n-type pillar (the n-type drift region) can be one order of magnitude higher than that of conventional drift region provided that the total charge of n-type pillar is designed to be balanced with charge in the p-type pillar. In order to fully realize the benefits of the super-junction, it is desirable to increase the packing density of the pillars to achieve a lower RSP. However, the minimum pillar widths that can be attained in practical device manufacturing set a limitation on the reducing the cell pitch and scaling the device.
Recently, inventions (see for example US application 20080191307 and US application 20080164518) have been disclosed to address this issue by incorporating fixed or permanent positive charge (QF) to balance the charge of a p-type pillar in a diode or voltage blocking structure. The permanent charge can also form an electron drift region in a power MOSFET, by forming an inversion layer along the interface between the oxide and P epi layer. By making use of that concept, the area scaling limitation due to inter-diffusion of p-type pillar and n-type pillar was mitigated. Consequently, a small cell pitch and high packing density of pillars and channels was achieved, reducing the device total on-resistance (and specific on-resistance RSP). In addition, the structure of FIG. 2 has a key advantage over conventional super-junction devices in that there is no JFET effect to limit the current so smaller cell pitches are highly desirable.